Multi­core processors have become the reference architecture for any modern computing system, including high­end servers, laptop/desktop PCs, as well as smartphones and other embedded systems. The consequence of this evolution of processors' design is that, today, the issue of synchronizing access to shared data challenges not only the specialists of parallel programming, but the mass of common programmers who wish to exploit, in a simple way, the full potential of modern architectures.

Transactional Memory (TM) [Herl93] answers precisely this urge of identifying paradigms to simplify concurrent programming and spare programmers from the complexity of classic locking schemes. By requiring programmers to only identify which code portions need to be executed atomically, and not how atomicity has to be enforced, TM can drastically simplify the development of parallel applications and abate their time­to­market and costs [Ross10,Pank11]

Over the last decade, TM has been a hot research topic in a number of interdisciplinary fields. However, research in the TM area has so far overlooked an essential aspect for any modern computer architecture: energy efficiency. Nowadays the theme of green computing is an ubiquitious concern, from data centers, which frequently perform on the limit of economically viable cooling systems, to mobile devices, whose computing power has been growing faster than batteries' capacities. Let alone the urge to reduce energy consumption, motivated by the environmental impact of electrical power production.

Yet, the matter of implementing high­performance energy­conscious TM remains largely an open issue. This is indeed a challenging problem, which involves understanding the complex relations between the parallelism degree of a TM application, the synchronization mechanisms of the TM framework, and the achievable performance/energy consumption.

In this project we aim to fill this relevant gap, by developing GreenTM, the first (to the best of our knowledge) energy­efficient TM system. To this end, GreenTM will combine, in an automatic and transparent fashion, alternative synchronization techniques under the guidance of innovative self­tuning schemes that will allow pursuing different trade­offs between performance and energy­consumption. More in detail, GreenTM will rely on the following key mechanisms:

  • Green Concurrency Control (GCC): most existing TM algorithms exploit speculation, which can lead to abort a large number of transactions and, consequently, to waste energy. The key innovative idea at the basis of GCC is to combine pessimistic, ahead­ of­time locking schemes, with runtime conflict detection mechanisms as supported by TM. By combining these 2 approaches, GCC aims to take the best of both: ahead­of­time locking allows to minimize energy waste by avoiding the concurrent execution of conflicting transactions; on the other hand, by relying on TM to detect conflicts among concurrent transactions, GCC can avoid using overly conservative locking strategies that ensure the absence of *any* atomicity violation (as in conventional lock allocation schemes), hence enhancing parallelism.
  • Dynamic switching between TMs: there exist fundamental trade­offs with regard to performance and energy­efficiency of existing TM algorithms; this is particularly true considering the recent introduction of hardware­based TM support in mainstream multiprocessors. GreenTM will leverage on these trade­offs and dynamically adapt the TM algorithm employed by the GCC to better fit the workload's characteristics with the goal of maximizing efficiency.
  • Concurrency throttling: GreenTM will integrate a novel combination of hardware/software mechanisms aimed at dynamically throttling parallelism of TM applications. To this end, we will exploit the ability of processors to adjust the operating frequency of their cores, as well as software techniques for adjusting the number of concurrently active application threads. This will allow to elastically tune the multiprogramming level depending on conflict probability, while prioritizing contending transactions (by increasing the frequency of the cores on which they run) to reduce aborts and consequent energy waste.

The above mechanisms will be regulated by an innovative self­tuning methodology, which will modularly combine analytical models, machine learning, and on­line exploration approaches. These self­tuning strategies will be driven by objective functions jointly considering performance and energy, a research direction so far unexplored in the area of TM.

Overall, this project is characterized by the exploration of recent trends in the industry and research. We propose several research lines to assess the viability of our ideas and obtain preliminary prototypes and results. This exploratory project will represent a first step and pave the way to future research in the emerging field of energy­efficiency in concurrent programming.

Journals

1. N. Diegues and Paolo Romano Self-Tuning Intel Restricted Transactional Memory Elsevier Parallel Computing, to appear

2. N. Diegues and Paolo Romano STI-BT: A Scalable Transactional Index IEEE Transactions on Parallel and Distributed Systems, to appear

3. N. Diegues and Paolo Romano Time-Warp: Efficient Abort Reduction in Transactional Memory ACM Transactions on Parallel Computing, to appear

4. N. Diegues and Paolo Romano Bumper: Sheltering Distributed Transactions from Conflicts Elsevier Future Generation Computer Systems, to appear

Conference Papers

1. Diego Didona and Paolo Romano Using Analytical Models to Bootstrap Machine Learning Performance Predictors The 21st IEEE International Conference on Parallel and Distributed Systems (ICPADS), December 2015

2. Shady Issa and Paolo Romano Green-CM: Energy efficient contention management for Transactional Memory 44th International Conference on Parallel Processing (ICPP), September 2015

3. Sebastiano Peluso, Roberto Palmieri, Paolo Romano, Binoy Ravindran and Francesco Quaglia Disjoint-Access Parallelism: Impossibility, Possibility, and Cost of Transactional Memory Implementations ACM Symposium on Principles of Distributed Computing (PODC), July 2015

4. N. Diegues and Paolo Romano Seer: Probabilistic Scheduling for Hardware Transactional Memory 27th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), June 2015

5. D. Didona, Paolo Romano Hybrid Machine Learning/Analytical Models for Performance Prediction: a Tutorial 6th ACM/SPEC International Conference on Performance Engineering (ICPE), Feb. 2015

6. D. Didona, Paolo Romano, F. Quaglia, E. Torre Combining Analytical Modeling and Machine-Learning to Enhance Robustness of Performance Prediction Models 6th ACM/SPEC International Conference on Performance Engineering (ICPE), Feb 2015

7. D. Didona and Paolo Romano Performance Modelling of Partially Replicated In-Memory Transactional Stores IEEE 22nd International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS'14), September 2014

8. N. Diegues and Paolo Romano and L. Rodrigues Virtues and Limitations of Commodity Hardware Transactional Memory The 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT 2014), August 2014

9. D. Rughetti, Paolo Romano, F. Quaglia and B. Ciciani Automatic Tuning of the Parallelism Degree in Hardware Transactional Memory The 20th International Conference on Parallel Processing (EuroPar 2014), August 2014

10. S. Peluso, R. Palmieri, Paolo Romano, B. Ravindran and F. Quaglia, Brief Announcement: Breaching the Wall of Impossibility Results on Disjoint-Access Parallel TM Proc. 28th International Symposium on Distributed Computing (DISC), Austin, TX, USA, October 2014

11. N. Diegues and Paolo Romano Self-Tuning Intel Transactional Synchronization Extensions The 11th International Conference on Autonomic Computing (ICAC 2014), Philadelphia, USA, 18-20 June 2014 BEST PAPER AWARD

12. N. Diegues and Paolo Romano STI-BT: A Scalable Transactional Index 34th International Conference on Distributed Computing Systems (ICDCS), Madrid, Spain, 30 June - 3 July 2014

In this page you can find the prototypes used in the experimental evaluation of the following papers:

Self-Tuning Intel Transactional Synchronization Extensions, N. Diegues and Paolo Romano, The 11th International Conference on Autonomic Computing, June 2014

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Virtues and Limitations of Commodity Hardware Transactional Memory, N. Diegues and Paolo Romano and L. Rodrigues, The 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT 2014), August 2014

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Time-Warp: Efficient Abort Reduction in Transactional Memory, N. Diegues and Paolo Romano, ACM Transactions on Parallel Computing (to appear)

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STI-BT: A Scalable Transactional Index, N. Diegues and Paolo Romano, IEEE Transactions on Parallel and Distributed Systems, to appear

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Green-CM: Energy efficient contention management for Transactional Memory, Shady Issa and Paolo Romano, 44th International Conference on Parallel Processing (ICPP), September 2015

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